Responsibilities
THE ROLE:
We are looking for an adaptive, self-motivated DFT design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The NBIO DFx team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.
THE PERSON:
Will have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
- Design verification of PCIe, UCIe, Chiplet Interconnect IPs for Analog & HSIO DFx features
- Build testbench components to support the next generation of NBIO IPs
- Estimate the time required to write the new feature tests and any required changes to the test environment
- Develop, maintain, and improve test libraries to support IP level testing
- Test coverage and test cost reduction analysis
- Train and mentor junior team members for PRBS DV execution
- Provide technical support to SoC and Post-Si teams to ensure successful bring up and enhance yield learning
PREFERRED EXPERIENCE:
- Understanding of Design for Test methodologies and DFT verification experience (e.g. JTAG 1149.x, IJTAG, PRBS, IO Loopback, etc.)
- Experienced with Verilog, System Verilog, and C++
- Developing UVM based verification frameworks and testbenches, processes and flows
- Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design
- Debug test failures to determine the root cause; work with design engineers to resolve design defects and correct any test issues
- Experience with ATE (Automatic Test Equipment) - ATE test pattern & test flow development, debug, test and characterization
- Design verification experience of High-Speed IO PHY and Controller logic is preferred
ACADEMIC CREDENTIALS:
- Bachelor’s or master’s degree in related discipline preferred
LOCATION: Markham, ON or Vancouver, BC
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Qualifications
Benefits offered are described: AMD benefits at a glance.
This posting is for an existing vacancy.
